coretile express 板在 versatile™ express 开发系统中提供主系统 cpu。coretile 必须与提供电源、配置和外设连接的主板 express uatx 板配对使用。
处理器子板 express 板与 versatile 产品系列中的前代产品的不同之处在于,其内存和 lcd 控制器等高带宽外设是与 arm 处理器一起在测试芯片中实现的。这会显示提升性能,使系统更适合进行软件基准测试并完全能运行 debian linux 等桌面操作系统。
处理器子板 express 系列支持的 arm 处理器有:
- cortex™-a15 mpcore
- cortex-a9 mpcore
- cortex-a7 mpcore
- cortex-a5 mpcore
处理器子板名称 |
coretile express |
coretile express 适用于 cortex-a9 |
coretile express 适用于 cortex-a5 |
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处理器子板名称(简称) | v2p-ca15x2_ca7x3 | v2p-ca9x4 | v2p-ca5x2s |
部件号 | v2p-ca15-0314a | v2p-ca9-0301a | v2p-ca5-0305a |
pcb 号 | hbi-0249 | hbi-0191 | hbi-0225 |
数据表 | 数据表 | 数据表 | 数据表 |
手册 | 用户手册 | 用户手册 | 用户手册 |
产品视频 | n/a | n/a | 视频 |
cpu 类型 |
cortex-a15 mpcore™ |
cortex-a9 mpcore | cortex-a5 mpcore |
cortex-a7 mpcore™ | |||
cpu 数量,速度 |
双核 ca15,1ghz 三核 ca7,800mhz |
四核,400mhz | 双核,100mhz |
cpu 版本 | r2p1,r0p1 | r0p1 | r0p1-rc0 |
协处理器 | neon™ | neon | neon |
l1 高速缓存 i/d | 32kb/32kb | 32kb/32kb | 32kb/32kb |
l2 高速缓存 | 1mb | 512kb | 256kb |
tcm | n/a | n/a | n/a |
sram(片上) | 64kb,64 位 | 16kb,64 位 | 64kb |
sdram | 2gb ddr2,32 位 | 1gb ddr2,32 位 | 1gb ddr2 sodimm |
sdram 速度 | 400mhz | 266mhz | 120mhz |
amba 总线类型 | axi | axi | axi |
内部 amba 总线速度 | 500mhz | 200mhz | 100mhz |
外部 amba 总线速度 | 50mhz (m) | 50mhz (m)、30mhz (s) | 40mhz (m)、40mhz (s) |
嵌入式跟踪 | 16/32 位,ptm,etb (4kb) | 16/32位,ptm,etb (8kb) | itm,etb (8kb) |
调试连接 | jtag 和 swd,20 针 dil | jtag 和 swd,20 针 dil | jtag 和 swd,20 针 dil |
the versatile™ express family development boards provide an
excellent environment for prototyping the next generation
system-on-chip designs. through a range of plug-in options,
hardware and software applications can be developed and
debugged.
the coretile express for the arm® cortex™-a15 mpcore™
and cortex-a7 processors is a test chip-based development
platform which implements a complete soc design around these
processors. this chip is the first commercially available silicon
that demonstrates the power-saving capabilities of arm big.
little™ processing it enables:
• exploration of the big.little architecture
• boot code, hypervisor, cluster-switching, device driver and
application software development
• software debug and development of software tools through
the on-chip coresight™ debug and trace infrastructure.
features
• processor subsystem
- dual cluster, big.little configuration
- 2 x arm cortex-a15 with vfp and neon,™ r2p1
- 1ghz operating speed
- caches: l1 32 kb, l2 1mb
- 3 x arm cortex-a7 with vfp and neon, r0p1
- 800mhz operating speed
- caches: l1 32kb, l2 512kb
- coresight etm/ptm per core 16kb etb
- dvfs control via system configuration controller
• amba® axi™ subsystem
- internal cci-400, 128-bit, 500mhz, r0p2
- internal nic301, 64-bit, 500mhz
- external amba axi: master port 64-bit, 50mhz
- ddr2 interface: dmc-400, 400mhz, r0p0
- 2gb of 32-bit ddr2 memory
- dmac: pl330, 128-bit
- static memory bus interface:pl354
- 32-bit 50mhz to motherboard
- boot from motherboard nor flash
- hdcld video controller: 1920 x 1080p, 60hz
• expansion support
- amba axi master link to expansion fpga daugherboard
• debug
- arm jtag: 20-way dil box header
- arm 32-bit parallel trace: dual 38-pin mictors
• simplified configuration via motherboard
- system appears as a usb flash drive on a pc
- fast programming and configuration
- configuration text files for system settings
- remote power control via rs232
deliverables
• v2p-ca15x2 ca7x3 daughterboard
• versatile express support dvd
• example amba axi subsystem design
- additional logictile required
• selftest software
• linux bsp